1. Field of the Invention
The present invention relates to computer systems, and more particularly, to a pipelined processor capable of executing a two-way conditional branch microinstruction with a single cycle of delay in addition to the execution of the microbranch itself, the additional delay cycle being required for changing direction of the pipeline.
2. Description of the Prior Art
A macroinstruction stored in a main memory comprises a plurality of microinstructions. When the macroinstruction is executed, each of the microinstructions are executed in sequence. Execution of the macroinstruction is complete when the last of the plurality of microinstructions is executed. When the main memory is addressed, the macroinstruction is retrieved and decoded into a starting microinstruction address in an instruction decode unit. The plurality of microinstructions are usually stored in a Read Only Memory (ROM), connected to the instruction decode unit, in the form of microcode. The retrieval of the macroinstruction from main memory necessarily requires the retrieval of the microinstructions from the ROM in response thereto, the microinstructions being executed, in sequence, by an Arithmetic Logic Unit (ALU).
As a result of the introduction of large scale integrated circuitry, circuits are embodied on integrated circuit chips. As technology advances, more and more circuits are required to be embodied on these integrated circuit chips. These circuits require implementation-space (otherwise referred to as "real estate") on the chips, but the available space on these chips is limited. Therefore, as the number of circuits, required to be embodied on the integrated circuit chips, increases, the available space, or, "real estate", on the chips becomes increasingly more scarce.
Due to the need for more space on the integrated circuit chips, it is necessary, in many cases, to reduce the size of the ROM for storage of the microinstructions. In order to reduce the size of the ROM, the ROM is subdivided into two parts: a microstore and a nanostore.
The subdivision of the ROM into the two parts solves one problem, the need for available "real estate" on a chip. However, it creates another problem, namely, an extra cycle of delay is introduced when the ALU executes a microbranch instruction.
A microbranch instruction is one which will branch to one of two directions depending upon the result of a decision. For example, in the quotient A/B, if B is not equal to 0, the quotient must be determined by one method, whereas, if B=0, the quotient must be determined by another method.
In a deeply pipelined processor, if the ROM is used to store the microinstructions, one cycle of delay is encountered when a microbranch instruction is being executed by the ALU, and the ALU branches to the "other method" for a solution to the current decision. However, if the microstore and the nanostore, collectively, store the microinstructions, in lieu of the ROM, two cycles of delay are encountered when the microbranch instruction is being executed by the ALU, and the ALU branches to the "other method" for a solution to the current decision.
As a result, in order to provide more available "real estate" on the integrated circuit chips, a performance sacrifice is necessary.